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| ZMD31050 Advanced Differential Sensor Signal Conditioner Data Sheet Rev. 1.06 / October 2009 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 Brief Description ZMD31050 is a CMOS integrated circuit for highly-accurate amplification and sensor-specific correction of bridge sensor signals. The device provides digital compensation of sensor offset, sensitivity, temperature drift and non-linearity by a 16-bit RISC micro controller running a correction algorithm with correction coefficients stored in non-volatile EEPROM. The ZMD31050 accommodates virtually any bridge sensor (e.g. piezo-resistive, ceramic-thick film or steel membrane based). In addition, the IC can interface a separate temperature sensor. The bi-directional digital interfaces (I2C, SPI, ZACwireTM) can be used for a simple PCcontrolled one-shot calibration procedure, in order to program a set of calibration coefficients into an on-chip EEPROM. Thus a specific sensor and a ZMD31050 are mated digitally: fast, precise and without the cost overhead associated with laser trimming, or mechanical potentiometer methods. Digital compensation of sensor offset, sensitivity, temperature drift and nonlinearity Accommodates nearly all bridge sensor types (signal spans from 1 up to 275mV/V processable) Digital one-shot calibration: quick and precise Selectable compensation temperature T1 source: bridge, thermistor, internal diode or external diode Output options: voltage (0V to 5V), 2 current (4mA to 20mA), PWM, I C, SPI, TM ZACwire (one-wire-interface), alarm Adjustable output resolution (up to 15 bits) versus sampling rate (up to 3.9kHz) Selectable bridge excitation: ratiometric voltage, constant voltage or constant current Input channel for separate temperature sensor Sensor connection and common mode check (Sensor aging detection) Operation temperature -40 to +125C (-40 to +150C derated, depending on product version) Supply voltage +2.7V to +5.5V Available in SSOP16 or as die Benefits No external trimming components required PC-controlled configuration and calibration via digital bus interface simple, low cost 85C; 0.25% FSO @ -40C to 125C) ZMD31050 Overview High accuracy (0.1% FSO @ -25C to Available Support Application kit (SSOP16 samples, calibration PCB, calibration software, technical documentation) Support for industrial mass calibration Quick circuit customization for large production volumes Features Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 2 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 Contents 1 Electrical Characteristics ............................................................................................................................ 5 1.1. Absolute Maximum Ratings ................................................................................................................ 5 1.2. Operating Conditions (Voltages related to VSS)............................................................................ 5 1.3. Build In Characteristics ....................................................................................................................... 6 1.4. Electrical Parameters 4 (Voltages related to VSS).......................................................................... 8 1.4.1. Supply / Regulation...................................................................................................................... 8 1.4.2. Analog Front End ......................................................................................................................... 8 1.4.3. DAC & Analog Output (Pin OUT)................................................................................................ 8 1.4.4. PWM Output (Pin OUT, IO1) ....................................................................................................... 8 1.4.5. Temperature Sensors (Pin IR_TEMP)......................................................................................... 8 1.4.6. Digital Outputs (IO1, IO2, OUT in digital mode) .......................................................................... 8 1.4.7. System Response........................................................................................................................ 9 1.5. Interface Characteristics ..................................................................................................................... 9 1.5.1. Multiport Serial Interfaces (I2C, SPI) ............................................................................................ 9 1.5.2. One Wire Serial Interface (ZACwireTM)........................................................................................ 9 Circuit Description .................................................................................................................................... 10 2.1. Signal Flow........................................................................................................................................ 10 2.2. Application Modes............................................................................................................................. 11 2.3. Analog Front End (AFE).................................................................................................................... 12 2.3.1. Programmable Gain Amplifier (PGA)......................................................................................... 12 2.3.2. Extended Zero Point Compensation (XZC) ............................................................................... 12 2.3.3. Measurement Cycle realized by Multiplexer .............................................................................. 13 2.3.4. Analog-to-Digital Converter........................................................................................................ 14 2.4. System Control.................................................................................................................................. 15 2.5. Output Stage ..................................................................................................................................... 16 2.5.1. Analog Output ............................................................................................................................ 17 2.5.2. Comparator Module (ALARM Output) ....................................................................................... 17 2.5.3. Serial Digital Interface................................................................................................................ 17 2.6. Voltage Regulator ............................................................................................................................. 18 2.7. Watchdog and Error Detection.......................................................................................................... 18 Application Circuit Examples.................................................................................................................... 19 ESD/Latch-Up-Protection ......................................................................................................................... 21 Pin Configuration and Package................................................................................................................ 21 Reliability .................................................................................................................................................. 22 Customization........................................................................................................................................... 22 Related Documents.................................................................................................................................. 22 Document Revision History ...................................................................................................................... 23 2 3 4 5 6 7 8 9 Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 3 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 List of Figures Figure 2.1 Figure 2.2. Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 5.1. Block Diagram of the ZMD31050................................................................................................10 Measurement cycle ZMD31050 ..................................................................................................13 Example 1 ...................................................................................................................................19 Example 2 ...................................................................................................................................19 Example 3 ...................................................................................................................................19 Example 4 ...................................................................................................................................19 Example 5 ...................................................................................................................................20 Pin Configuration.........................................................................................................................21 List of Tables Table 1.1 Table 1.2 Table 1.3 Table 1.4 Table 1.5 Table 1.6 Table 1.7. Table 2.1 Table 2.2 Table 2.3 Table 2.4. Table 2.5. Table 5.1. Absolute Maximum Ratings ..........................................................................................................5 Operating Conditions ....................................................................................................................5 Build In Characteristics .................................................................................................................6 Cycle Rate versus A/D-Resolution................................................................................................7 PWM Frequency ...........................................................................................................................7 Electrical Parameters ....................................................................................................................8 Interface Characteristics ...............................................................................................................9 Adjustable gains, resulting sensor signal spans, and common mode ranges ............................12 Extended Zero Point Compensation Range ...............................................................................13 Output Resolution versus Sample Rate......................................................................................14 Output configurations overview...................................................................................................16 Analog output configuration ........................................................................................................17 Pin Configuration.........................................................................................................................21 Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 4 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 1 1.1. No. 1.1.1 1.1.2 1.1.3 1.1.4 1.1.5 Electrical Characteristics Absolute Maximum Ratings Absolute Maximum Ratings Parameter Digital Supply Voltage Analog Supply Voltage Voltage at all analog and digital I/O - Pins Voltage at Pin FBP Storage temperature Symbol VDDAMR VDDAAMR VA_I/O, VD_I/O VFBP_AMR TSTG 1 Table 1.1 min -0.3 -0.3 -0.3 -1.2 -45 typ max 6.5 6.5 VDDA +0.3 VDDA +0.3 150 Unit V DC V DC V DC V DC C Conditions To VSS To VSS Exception see 1.1.4 4 mA to 20mA - Interface 1.2. No. 1.2.1 1.2.2.1 1.2.2.2 1.2.3 1.2.4 1.2.5 1.2.6 1.2.7 1.2.8 1.2.9 1.2.10 1.2.11 1.2.12 Operating Conditions Parameter Ambient temperature advanced performance Ambient temperature Automotive range Ambient temperature Extended automotive range Ambient temperature EEPROM programming EEPROM programming cycles Data retention (EEPROM) Analog Supply Voltage Analog Supply Voltage advanced performance Digital Supply Voltage External Supply Voltage Common mode input range Input Voltage Pin FBP Sensor Bridge Resistance (Voltages related to VSS) Symbol min -25 -40 -40 -25 typ max 85 125 150 85 100 15 a V DC V DC VDDA V DC V DC VADC_ REF V DC k k Full temperature range CurrentLoop-IF 4 to 20mA Averaged temp < 85C Ratiometric mode Ratiometric mode External powered Voltage regulator mode with ext. JFET Depends on gain adjust, refer chapter 2.3.1. Unit C C C C Operation life time < 1000h @ 125 to 150C Conditions TQI = -25 to 85C TQC = 0 to 70C Table 1.2 Operating Conditions TADV TAMB_TQA TAMB_TQE TAMB_EEP VDDA VDDAADV VDD VSUPP VIN_CM VIN_FBP RBR RBR_CL 2.7 4.5 2.7 VDDA + 2V 0.21 -1 3.0 5.0 1 5.5 5.5 1.05 2 0.76 VDDA 25.0 25.0 1 2 Default configuration: 2 order AD-conversion, 13Bit Resolution, gain >=210, fclk<=2.25MHz Maximum depending on breakdown voltage of external JFET, notice application hints in related application note. Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. nd 5 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 No. 1.2.13 Parameter Reference Resistor for Bridge Current Source * Stabilization Capacitor * VDD Stabilization Capacitor * Maximum allowed load capacitance at OUT3 Minimum allowed load resistance Maximum allowed load capacitance at VGATE Symbol RBR_RE F CVDDA CVDD CL_OUT RL_OUT CL_VGA TE 2 10 min 0.07 typ max Unit RBR Conditions Leads to IBR = VDDA / (16*RBR_REF) Between VDDA and VSS, external Between VDD and VSS, external Output Voltage mode Output Voltage mode Summarized to all potentials 1.2.14 1.2.15 1.2.16 1.2.17 1.2.18 50 02 100 100 470 470 50 nF nF nF k nF 1.3. No. 1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 Build In Characteristics Build In Characteristics Parameter Selectable Input Span, Pressure Measurement Analog Offset Comp Range (6 Bit setting) A/D Resolution D/A Resolution PWM - Resolution Bias current for external temperature diodes Sensitivity internal temperature diode Clock frequency rADC rDAC rPWM ITS STT_SI fCLK 9 8 2800 1* 18 320 0 2 Symbol VIN_SP min 2 -20 -25 9 11 12 40 3600 4* typ max 280 20 25 15 Unit mV/V count ADJREF:BCUR=7 Bit Bit Bit A ppm f.s. /K MHz Raw values - without conditioning guaranteed adjustment range 3 Bit setting 4 Table 1.3 Conditions Refer chapter 2.3.1. @ analogue output No measurement in mass production, parameter is guarantied by design and/or quality observation No limitations with an external connection between VDDA and VBR 2 Lower stabilization capacitors can increase noise level at the output 3 If used, consider special requirements of ZACwireTM single wire interface stated in "Functional Description" chapter 4.3 4 st Resolution of 15bit is not applicable for 1 order ADC and not recommended for sensors with high nonlinearity behaviour 1 Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 6 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 1.3.9 Cycle Rate versus A/D-Resolution (linear related to master clock frequency1 - values calculated at exact 2 MHz ) Table 1.4 Cycle Rate versus A/D-Resolution Resolution rADC Bit 9 10 11 12 13 14 2 11 12 13 14 15 Hz 1302 781 434 230 115 59 3906 3906 1953 1953 977 Conversion Cycle fCYC fCLK=2MHz fCLK=2.25MHz Hz 1465 879 488 259 129 67 4395 4395 2197 2197 1099 ADC Order OADC 1 1.3.10 PWM Frequency * Table 1.5 PWM Resolution rPWM [Bit] 9 10 11 12 1 3906 1953 977 488 PWM Frequency PWM Freq./Hz at 2 MHz Clock1 Clock Divider 0,5 1953 977 488 244 0,25 977 488 244 122 0,125 488 244 122 61 1 4395 2197 1099 549 PWM Freq./Hz at 2.25 MHz Clock2 Clock Divider 0,5 2197 1099 549 275 0,25 1099 549 275 137 0,125 549 275 137 69 1 2 No measurement in mass production, parameter is guarantied by design and/or quality observation Internal RC - Oscillator: coarse adjustment to1, 2 and 4 MHz, fine tuning +/- 25% , external clock is also possible Internal RC - Oscillator: coarse adjustment to1.125, 2.25 and 4.5 MHz, fine tuning +/- 25% , external clock is also possible Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 7 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 1.4. No. 1.4.1.1 Electrical Parameters 4 Electrical Parameters Parameter Supply current Symbol 1.4.1. ISUPP min typ 2.5 max 4 (Voltages related to VSS) Unit mA Conditions Without bridge and load current, fCLK2.4MHz, Bias-Adjust4 Without bridge current, fCLK1.2MHz, Bias-Adjust1 ppm/K 1 Table 1.6 Supply / Regulation 1.4.1.2 1.4.1.2 Supply current for current loop Temperature Coeff. Voltage Reference * Parasitic differential input offset current * Output signal range Output DNL Output INL Output slew rate * Short circuit current * ISUPP_CL TCREF 1.4.2. -200 2.0 50 2.75 200 Analog Front End -2 to 10 0.025 2 to 10 0.975 0.95 4 0.1 5 0 10 20 1 nA Temp. range 5.2.2., TADV 1.4.2.1 IIN_OFF 1.4.3. DAC & Analog Output (Pin OUT) 1.4.3.1 1.4.3.2 1.4.3.3 1.4.3.4 1.4.3.5 1.4.3.6 VOUT_SR DNLOUT INLOUT SROUT IOUT_max VOUT_ADR 1.4.4. VDDA LSB LSB V/s mA Voltage Mode, RLOAD > 2K 2 VDDAADV ,TADV VDDAADV ,TADV 3 Voltage mode, CL<20nF, using conditions of 1.4.3.1. 2048 steps Addressable output signal range * PWM high voltage PWM low voltage PWM output slew rate * VDDA PWM Output (Pin OUT, IO1) 0.9 0.1 15 75 210 1.4.4.1 1.4.4.2 1.4.4.3 1.4.5.1 VPWM_H VPWM_L SRPWM 1.4.5. STTS_E VDDA VDDA V/s RL > 10 k RL > 10 k CL < 1nF At rADC = 13 Bit Temperature Sensors (Pin IR_TEMP) Sensitivity external diode / resistor meas. 1.4.6. Output-High-Level Output-Low-Level Output Current V/LS B VDDA Digital Outputs (IO1, IO2, OUT in digital mode) VDOUT_H VDOUT_L IDOUT 4 0.9 0.1 RL > 1 k RL > 1 k 1.4.6.1 1.4.6.2 1.4.6.3 VDDA mA 1 2 Recommended bias adjust <= 4, notice application hints and power consumption adjust constraints in related application note Derated performance in lower part of supply voltage range (2.7 to 3.3V): 2.5 to 5%VDDA & 95 to 97.5%VDDA 3 Output linearity and accuracy can be enhanced by additional analog output stage calibration 4 nd Default configuration: 2 order AD-conversion, 13Bit Resolution, gain >=210, fclk<=2.25MHz No measurement in mass production, parameter is guarantied by design and/or quality observatio Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 8 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 No. 1.4.7.1 1.4.7.2 1.4.7.3 Parameter Startup time 1 ,* Response time * Overall accuracy (deviation from ideal line including INL, gain and offset errors) 2 ,* Analog Output Noise Peak-to-Peak * Analog Output Noise RMS * Ratiometricity Error Symbol 1.4.7. tSTA tRESP ACOUT 2 1.66 2.66 min typ max 5 3.66 0.10 0.25 0.50 Unit ms 1/fCON % % % Conditions PowerOn to 1st measure result at output 66% jump, refer 2.3.4 for fCON TADV & VDDAADV TAMB_TQA & VDDAADV System Response @ current-loop-OUT & TADV & VDDAADV (refer also application note AN05 of ZMD31050) 1.4.7.4 1.4.7.5 1.4.7.6 VNOISE,PP VNOISE,RMS REOUT_5V REOUT_3V 10 3 500 1000 mV mV ppm ppm Shorted inputs, gain<=210 bandwidth 10kHz Shorted inputs, gain<=210 bandwidth 10kHz 5% respect. 1000ppm 10% (5V) 5% respect. 2000ppm 10% (3V) 1.5. No. 1.5.1.1 1.5.1.2 1.5.1.3 1.5.1.4 1.5.1.5 1.5.1.6 1.5.1.7 1.5.2.1 1.5.2.2 1.5.2.3 1.5.2.4 1.5.2.5 Interface Characteristics Interface Characteristics Parameter 1.5.1. Input-High-Level Input-Low-Level Output-Low-Level Load capacitance @ SDA Clock frequency SCL Pull-up Resistor Input capacitance (each pin) 1.5.2. OWI start window Pull-up resistance master OWI load capacitance Voltage level Low Voltage level High 3 Table 1.7. Symbol VI2C_IN_H VI2C_IN_L VI2C_OUT_L CSDA fSCL RI2C_PU CI2C_IN ROWI_PU ROWI_PU COWI_LOAD VOWI_L VOWI_H min 0.7 0 typ 1 max 2 Unit VDDA VDDA VDDA pF kHz pF ms Conditions Multiport Serial Interfaces (I C, SPI) 0.3 0.1 400 400 500 10 20 330 0.08 0.2 0.75 fCLK 2MHz valid for SPI as well One Wire Serial Interface (ZACwireTM) tOWI_BIT / ROWI_PU VDDA VDDA 20s < tOWI_BIT < 100s 1 OWI - start window disabled, according default configuration (depends on resolution and configuration - start routine begins approximately 0.8ms after power on) 2 Accuracy better than 0.5% requires offset and gain calibration for the analog output stage, Parameter only for ratiometric output. Refer "ZMD31050_FunctionalDescription_Rev_*.pdf" for other output configurations. 3 Internal clock frequency fCLK has to be in minimum 5 times higher than communication clock frequency * No measurement in mass production, parameter is guarantied by design and/or quality observatio Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 9 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 2 2.1. Circuit Description Signal Flow The ZMD31050's signal path is partly analog (blue) and partly digital (red). The analog part is realized differential - this means internal is the differential bridge sensor signal also handled via two signal lines, which are rejected symmetrically around a common mode potential (analog ground = VDDA/2). Consequently it is possible to amplify positive and negative input signals, which are located in the common mode range of the signal input. Figure 2.1 Block Diagram of the ZMD31050 PGA MUX ADC CMC DAC FIO1 FIO2 SIF PCOMP EEPROM TS ROM PWM Programmable gain amplifier Multiplexer Analog-to-digital converter Calibration microcontroller Digital-to-analog converter Flexible I/O 1: analog out (voltage/current), PWM2, ZACwireTM (one-wire-interface) Flexible I/O 2: PWM1, SPI data out, SPI slave select, Alarm1, Alarm2 Serial interface: I2C data I/O, SPI data in, clock Programmable comparator Non volatile memory for calibration parameters and configuration On-chip temperature sensor (pn-junction) Memory for correction formula and -algorithm PWM module The differential signal from the bridge sensor is pre-amplified by the programmable gain amplifier (PGA). The Multiplexer (MUX) transmits the signals from bridge sensor, external diode or separate temperature sensor Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 10 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 to the ADC in a certain sequence (instead of the temperature diode the internal pn-junction (TS) can be used optionally). Afterwards the ADC converts these signals into digital values. The digital signal correction takes place in the calibration micro-controller (CMC). It is based on a special correction formula located in the ROM and on sensor-specific coefficients (stored into the EEPROM during calibration). Dependent on the programmed output configuration the corrected sensor signal is output as analog value, as PWM signal or in digital format (SPI, I2C, ZACwireTM ). The output signal is provided at 2 flexible I/O modules (FIO) and at the serial interface (SIF). The configuration data and the correction parameters can be programmed into the EEPROM via the digital interfaces. The modular circuit concept enables fast custom designs varying these blocks and, as a result, functionality and die size. 2.2. Application Modes For each application a configuration set has to be established (generally prior to calibration) by programming the on-chip EEPROM regarding to the following modes: Sensor channel Sensor mode: ratiometric voltage or current supply mode. Input range: The gain of the analog front end has to be chosen with respect to the maximum sensor signal span and to this has also adjusted the zero point of the ADC Additional offset compensation: The extended analog offset compensation has to be enabled if required, e.g. if the sensor offset voltage is near to or larger than the sensor span. Resolution/response time: The A/D converter has to be configured for resolution and conversion scheme (1st or 2nd order). These settings influence the sampling rate, signal integration time and this way the noise immunity. Ability to invert the sensor bridge inputs Analog output Choice of output method (voltage value, current loop, PWM) for output register 1. Optional choice of additional output register 2: PWM via IO1 or alarm out module via IO1/2. Digital communication: The preferred protocol and its parameter have to be set. Temperature The temperature measure source for the temperature correction has to be chosen. The temperature measure source T1 sensor type for the temperature correction has to be chosen (only T1 is usable for correction!!!) Optional: the temperature measure channel as the second output has to be chosen. Supply voltage : For non-ratiometric output the voltage regulation has to be configured. Note: Not all possible combinations of settings are allowed (see section 2.5). The calibration procedure must include Set of coefficients of calibration calculation and, depending on configuration, Adjustment of the extended offset compensation, Zero compensation of temperature measurement, Adjustment of the bridge current and, if necessary, Set of thresholds and delays for the alarms and the reference voltage. Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 11 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 2.3. Analog Front End (AFE) The analog front end consists of the programmable gain amplifier (PGA), the multiplexer (MUX) and the analog-to-digital converter (ADC). 2.3.1. Programmable Gain Amplifier (PGA) The following tables show the adjustable gains, the processable sensor signal spans and the allowed common mode range. Table 2.1 No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Adjustable gains, resulting sensor signal spans, and common mode ranges Gain Amp1 30 30 15 15 15 7,5 7,5 3,75 3,75 1 1 1 1 Gain Amp2 7 4,66 7 4,66 3,5 4,66 3,5 4,66 3,5 7 4,66 3,5 1,4 Gain Amp3 2 2 2 2 2 2 2 2 2 2 2 2 2 Max. span VIN_SP in mV/V 2 3 4 6 8 12 16 24 32 50 80 100 280 Input range VIN_CM in % VDDA 43 - 57 40 - 59 43 - 57 40 - 59 38 - 62 40 - 59 38 - 62 40 - 59 38 - 62 43 - 57 40 - 59 38 - 62 21 - 76 PGA Gain aIN 420 280 210 140 105 70 52,5 35 26,3 14 9,3 7 2,8 2.3.2. Extended Zero Point Compensation (XZC) The ZMD31050 supports two methods of sensor offset cancellation (zero shift): Digital offset correction XZC - an analog cancellation for large offset values (up to approx 300% of span) The digital sensor offset correction will be processed at the digital signal correction/conditioning by the CMC. The analog sensor offset pre-compensation will be needed for compensation of large offset values, which would be overdrive the analog signal path by uncompensated gaining. For analog sensor offset precompensation a compensation voltage will be added in the analog pre-gaining signal path (coarse offset removal). The analog offset compensation in the AFE can be adjusted by 6 EEPROM bits. It allows an analog zero point shift up to 300% of the processable signal span. The zero point shift of the temperature measurements can also be adjusted by 6 EEPROM bits 20...+20) and is calculated by: VXZC / VDDBR= k * ZXZC / ( 20 * aIN) (ZXZC= - Bridge in voltage mode, refer "ZMD31050 Functional description" for usable input signal/common mode range at bridge in current mode Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 12 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 Table 2.2 PGA gain aIN 420 280 210 140 105 70 52,5 35 26,3 14 9,3 7 2,8 Extended Zero Point Compensation Range Max. span VIN_SP in mV/V 2 3 4 6 8 12 16 24 32 50 80 100 280 Calculation factor k 3,0 1,833 3,0 1,833 1,25 1,833 1,25 1,833 1,25 3,0 1,833 1,25 0,2 Offset shift per step in % full span 15% 9% 15% 9% 6% 9% 6% 9% 6% 15% 9% 6% 1% Approx. maximum offset shift in mV/V +/- 7 +/- 6 +/- 14 +/- 12 +/- 12 +/- 24 +/- 22 +/-48 +/- 45 +/- 180 +/- 160 +/- 140 +/- 60 Approx. maximum shift in [% VIN_SP] (@ 20 steps) 330 200 330 200 140 200 140 200 140 330 200 140 22 Note: ZXZC can be adjusted in range -31 to 31, parameters are guaranteed only in range -20 to 20. 2.3.3. Measurement Cycle realized by Multiplexer Internal offset of the input channel measured by input short circuiting Bridge temperature signal measured by external and internal diode (pn-junction) Bridge temperature signal measured by bridge resistors Start routine Temperature measurement by external thermistor Pre-amplified bridge sensor signal PMC Pressure measurement 1 PMC 1 PMC 1 PMC * T2E T2E PMC * T2E T2E PMC 1 Figure 2.2. Temp 1 auto zero Pressure measurement Temp 1 measurement Pressure measurement Pressure auto zero Pressure measurement Temp 2 auto zero Pressure measurement Temp 2 measurement Pressure measurement Common mode voltage Measurement cycle ZMD31050 The Multiplexer selects, depending on EEPROM settings, the following inputs in a certain sequence. The complete measurement cycle is controlled by the CMC. The cycle diagram at the right shows its principle structure. The EEPROM adjustable parameters are: Pressure measurement count, PMC=<1,2,4,8,16,32,64,128> Temperature 2 measurement enable, T2E=<0,1> After Power ON the start routine is called. It contains the pressure and auto zero measurement. When enabled it measures the temperature and its auto zeros. Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 13 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 2.3.4. Analog-to-Digital Converter The ADC is a charge balancing converter in full differential switched capacitor technique. It can be used as first or second order converter: In the first order mode it is inherently monotone and insensitive against short and long term instability of the clock frequency. The conversion cycle time depends on the desired resolution and can be roughly calculated by: tCYC_1 = 2 rADC s The available ADC-resolutions are rADC = <9,10,11,12,13,14>. In the second order mode two conversions are stacked with the advantage of much shorter conversion cycle time and the drawback of a lower noise immunity caused by the shorter signal integration period. The conversion cycle time at this mode is roughly calculated by: tCYC_2 = 2 (rADC +3)/2 s The available ADC-resolutions are rADC = <11,12,13,14,15>. The result of the AD conversion is a relative counter result corresponding to the following equation: ZADC = 2 ZADC: VADC_DIFF: VADC_REF: RSADC: rADC * [(VADC_DIFF /VADC_REF) + (1 - RSADC)] Number of counts (result of the conversion) Differential input voltage of ADC (= aIN * VIN_DIFF) Reference voltage of ADC (= VBR or VDDA) Digital ADC Range Shift (RSADC = 15/16, 7/8, 3/4, 1/2, controlled by the EEPROM content) With the RSADC value a sensor input signal can be shifted in the optimal input range of the ADC. The Pin Table 2.3 ADC Order OADC 1 1 1 1 Output Resolution versus Sample Rate Maximum Output Resolution rADC Bit 9 10 11 12 1 Sample Rate fCON rPWM Bit 9 10 11 12 fCLK=2MHz Hz 1302 781 434 230 fCLK =2.25MHz Hz 1465 879 488 259 Digital-OUT Bit 9 10 11 12 Analog-OUT Bit 9 10 11 11 1 ADC Resolution should be 1 to 2 Bits higher then applied Output Resolution Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 14 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 ADC Order OADC 1 1 2 2 2 2 2 2 rADC 1 Bit 13 14 10 11 12 13 14 15 Maximum Output Resolution Digital-OUT Bit 13 14 10 11 12 13 14 15 Analog-OUT Bit 11 11 10 11 11 11 11 11 rPWM Bit 12 12 10 11 12 12 12 12 Sample Rate fCON fCLK=2MHz Hz 115 59 3906 3906 3906 1953 1953 977 fCLK =2.25MHz Hz 129 67 4395 4395 4395 2197 2197 1099 2.4. System Control The system control has the following features: Control of the I/O relations and of the measurement cycle regarding to the EEPROM-stored configuration data 16 bit correction calculation for each measurement signal using the EEPROM stored calibration coefficients and ROM-based algorithms Started by internal POC, internal clock - generator or external clock For safety improvement the EEPROM data are proved with a signature within initialization procedure, the registers of the CMC are steadily observed with a parity check. Once an error is detected, the error flag of the CMC is set and the outputs are driven to a diagnostic value Note: The conditioning includes up to third order sensor input correction. The available adjustment ranges depend on the specific calibration parameters, a detailed description will be issued later. To give a rough idea: Offset compensation and linear correction are only limited by the loose of resolution it will cause, the second order correction is possible up to about 20% full scale difference to straight line, third order up to about 10% (ADC resolution = 13bit). The temperature calibration includes first and second order correction and should be fairly sufficient in all relevant cases. ADC resolution influences also calibration possibilities - 1 bit more resolution reduces calibration range by approximately 50%. 1 ADC Resolution should be 1 to 2 Bits higher then applied Output Resolution Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 15 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 2.5. Output Stage Output configurations overview Used I/O pins OUT IO1 ALARM1 ALARM2 ALARM1 PWM1 PWM1 Analog Analog Analog Analog Analog Analog PWM2 PWM2 PWM2 PWM2 PWM2 PWM2 X X X X X X X X X Analog Analog Analog PWM2 PWM2 PWM2 ALARM1 PWM1 PWM1 Data out Data out ALARM1 Data out PWM1 Data out Data out ALARM1 Data out PWM1 Data out Data out ALARM1 Data out PWM1 ALARM2 Slave select Slave select Slave select Slave select Slave select Slave select Slave select Slave select Slave select ALARM1 ALARM2 ALARM2 ALARM1 PWM1 PWM1 ALARM2 ALARM1 ALARM2 ALARM2 ALARM2 ALARM2 Table 2.4. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 Used SIF I2C X X X X X X X X X X X X X X X X X X SPI IO2 SDA Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data I/O Data in Data in Data in Data in Data in Data in Data in Data in Data in - The ZMD31050 provides the following I/O pins: OUT, IO1, IO2 and SDA. Via these pins the following signal formats can be output: Analog (voltage/current), PWM, Data (SPI/I2C), Alarm. The following values can be provided at the O/I pins: bridge sensor signal, temperature signal 1, temperature signal 2, alarm. Note: The Alarm signal only refers to the bridge sensor signal, but never to a temperature signal. Due to the necessary pin sharing there are restrictions to the possible combinations of outputs and interface connections. The table beside gives an overview about possible combinations. Note: In the SPI mode the pin IO2 is used as Slave select. Thus no Alarm 2 can be output in this mode. Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 16 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 2.5.1. Analog Output For the analog output 3 registers of 15 bit depth are available, which can store the actual pressure and the results of temperature measurement 1 and 2. Each register can be independently switched to one of two output slots connected to the Pin OUT and IO1 respectively. In these output slots different output modules are available according to the following table: Table 2.5. Analog output configuration Output slot: Voltage PWM OUT x x x IO1 The voltage module consists of an 11bit resistor string - DAC with buffered output and a subsequent inverting amplifier with class AB rail-to-rail OpAmp. The two feedback nets are connected to the Pins FBN and FBP. This structure offers wide flexibility for the output configuration, for example voltage output and 4 mA to 20 mA current loop output. To short circuit the analog output against VSS or VDDA does not damage the ZMD31050. The PWM module provides pulse streams with signal dependent duty cycle. The PWM - frequency depends on resolution and clock divider. The maximum resolution is 12 bit, the maximum PWM - frequency is 4 kHz (9 bit). If both, second PWM and SPI protocol are activated, the output pin IO1 is shared between the PWM output and the SPI_SDO output of the serial interface (interface communication interrupts the PWM output). 2.5.2. Comparator Module (ALARM Output) The comparator module consists of two comparator channels connectable to IO1 and IO2 respectively. Each of them can be independently programmed referring to the parameters threshold, hysteresis, switching direction and on/off - delay. Additional a window comparator mode is available. 2.5.3. Serial Digital Interface The ZMD31050 includes a serial digital interface which is able to communicate in three different communication protocols - I2CTM, SPITM and ZACwireTM (one wire communication). In the SPI mode the pin IO2 operates as slave select input, the pin IO1 as data output. Initializing Communication After power-on the interface is for about 20ms (start window) in the state ZACwire. During the start window it is possible to communicate via the one wire interface (pin OUT). Detecting a proper request inside the start window the interface stays in the state ZACwire. This state can be left by certain commands or a new power-on. If during the start window no request happens then the serial interface switches to I2C or SPI mode (depending on EEPROM settings). The OUT pin is used as analog output or as PWM output (also depending on EEPROM settings). The start window can generally be disabled (or enabled) by a special EEPROM setting. For detailed description of the serial interfaces see "ZMD31050 Functional Description". Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 17 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 2.6. Voltage Regulator For ratiometric applications 3V to 5V (10%) the external supply voltage can be used for sensor element biasing. If an absolute analog output is desired then the internal voltage regulator with external power regulation element (JFET) can be used. The regulation is bandgap reference based and designed for an external supply voltage VSUPP in the range of 7V to 40VDC. The internal supply and sensor bridge voltage can be varied between 3V and 5.5V in 4 steps with the voltage regulator. 2.7. Watchdog and Error Detection The ZMD31050 detects various possible errors. A detected error is signalized by changing in a diagnostic mode. In this case the analog output is set to the high or low level (maximum or minimum possible output value) and the output registers of the digital serial interface are set to a significant error code. A watchdog oversees the continuous working of the CMC and the running measurement loop. A check of the sensor bridge for broken wires is done permanently by two comparators watching the input voltage of each input [(VSSA + 0.5V) to (VDDA - 0.5V)]. Add on the common mode voltage of the sensor is watched permanently (sensor aging). Different functions and blocks in digital part are watched like RAM-, ROM,- EEPROM- and Register content continuously, the document "ZMD31050 Functional Description" contains in chapter 1.3.4 a detailed description of all watched blocks and methods of messaging of errors. Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 18 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 3 Application Circuit Examples Figure 3.1 Example 1 Typical ratiometric measurement with voltage output, temperature compensation via external diode, internal VDD regulator and active sensor connection check (bridge must not be at VDDA) Figure 3.2 Example 2 0V to 10V output configuration, supply regulator (external JFET), temperature compensation via internal diode and bridge in voltage mode Figure 3.3 Example 3 Absolute voltage output, supply regulator (external JFET), constant current excitation of the sensor bridge, temperature compensation by bridge voltage drop measurement, internal VDD regulator without ext. capacitor Figure 3.4 Example 4 Ratiometric bridge differential signal measurement, 3- wire connection for end of line calibration at pin OUT (ZACwireTM), additional temperature measurement with external thermistor and PWM-output at pin IO1 Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 19 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 VDDA = 5V ZD 7.5 V 0.1F 0.1F 10 nF 9 FBN 10OUT 11FBP 12 IR_TEMP 13 VBR 14 VINP 15 VSS 16 VINN VDD8 SDA 7 SCL6 IO25 IO14 VGATE 3 IN32 VDDA1 R e 150 Rsens 50 +7V to +40 V VSUPP (Current Loop+) Serial Interface Flexible I/Os Ground ( Current Loop-) 4 to 20mA Figure 3.5 Example 5 Two-wire-(4 to 20) mA configuration [(7 to 40) V], temperature compensation via internal diode Hints: It is possible to combine or split connectivity of different application examples. For VDD generation ZMDI recommends to use internal supply voltage regulator with external capacitor. Notice additional application notes for usage of supply voltage regulation property (non ratiometric mode) and current loop output mode. Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 20 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 4 ESD/Latch-Up-Protection All pins have an ESD protection of >2000V (except the pins INN, INP and FBP with > 1200V) and a latch-up protection of 100mA or of +8V/ -4V (to VSS/VSSA) - refer chapter 5 for details and restrictions. ESD protection referred to the human body model is tested with devices in SSOP16 packages during product qualification. The ESD test follows the human body model with 1.5kOhm/100pF based on MIL 883, method 3015.7. 5 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Configuration and Package Pin Configuration Description Positive analog supply voltage Resistive temp sensor IN & external clock IN Gate voltage for external regulator FET SPI data out & ALARM1 & PWM1 Output SPI chip select & ALARM2 IC clock & SPI clock Data IO for IC & data IN for SPI Positive digital supply voltage Negative feedback connection output stage Analog output & PWM2 Output & one wire interface i/o Positive feedback connection output stage Current source resistor i/o & temp. diode in Bridge top sensing in bridge current out Positive input sensor bridge Negative supply voltage Negative input sensor bridge Remarks Supply Analog IN Analog OUT Digital IO Digital IO Digital IN, pull-up Digital IO, pull-up Supply Analog IO Analog OUT & dig. IO Analog IO Analog IO Analog IO Analog IN Ground Analog IN Free accessibility Free accessible (latch-up related) Only connection to external FET Free accessibility Free accessibility Free accessibility Free accessibility Only capacitor to VSS allowed, otherwise no application access Free accessibility Free accessibility Free accessibility Circuitry secures potential inside of VSS-VDDA range, otherwise no application access Only short to VDDA or connection to sensor bridge, otherwise no application access Free accessibility Latch-Up related Application Circuit Restrictions and/or Remarks Name VDDA IN3 VGATE IO1 IO2 SCL SDA VDD FBN OUT FBP IR_TEM P VBR VINP VSS VINN Table 5.1. The standard package of the ZMD31050 is a SSOP16 (5.3mm body width) with lead-pitch 0.65mm: Figure 5.1. Pin Configuration Pin-Nr 9 10 11 12 13 14 15 16 Data Sheet Rev. 1.06 October 2009 Pin-Name FBN OUT FBP IR_TEMP VBR VINP VSS VINN Pin-Name VDD SDA SCL IO2 IO1 VGATE IN3 VDDA Pin-Nr 8 7 6 5 4 3 2 1 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 16 1 ZMD U23456 abcd xxxx YYWW 21 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 6 Reliability A reliability investigation according to the in-house non-automotive standard will be performed. A fit rate < 5fit (temp=55C, S=60%) is guaranteed. A typical fit rate of the C7A-technologie, which is used for ZMD30150, is 2.5fit . 7 Customization For high-volume applications, which require an up- or downgraded functionality compared to the ZM31050, ZMDI can customize the circuit design by adding or removing certain functional blocks. For it ZMDI has a considerable library of sensor-dedicated circuitry blocks. Thus ZMDI can provide a custom solution quickly. Please contact ZMDI for further information. 8 Related Documents File Name ZMD31050_Feature_Sheet_rev_x_yy.pdf ZMD31050_FunctionalDescription_rev_x_yy.pdf ZMD31050_Application_Kit_Description_rev_x_yy.pdf Document ZMD31050 Feature Sheet ZMD31050 Functional Description ZMD31050 Evaluation Kit Description ZMD31050 Development Status Report (including parts identification table) ZMD31050 Application Notes Visit ZMDI's website www.zmdi.com or contact your nearest sales office for the latest version of these documents. Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 22 / 23 Data Sheet Advanced Differential Sensor Signal Conditioner ZMD31050 9 1.00 1.01 1.02 1.03 Document Revision History Revision Date Description First release of document. Headlines and footnotes at all pages updated 5.5.1.7 - Input capacitance of digital interface pins added 5.4 - note 4 "Default Configuration" added 5.4.7.3 - overall accuracy / values & conditions for current loop output inserted 6. - Reliability / fit rate values added adjust to new ZMDI template changed "Related Documents" and "Document Revision History" so that information is included in table change to ZMDI denotation 1.04 1.05 September 2009 October 2009 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. ZMD AG assumes no obligation regarding future manufacture unless otherwise agreed to in writing. The information furnished hereby is believed to be true and accurate. However, ZMD AG shall not be liable to any customer, licensee or any other third party for any damages in connection with or arising out of the furnishing, performance or use of this technical data. Sales Offices and Further Information ZMD AG Grenzstrasse 28 01109 Dresden Germany www.zmdi.com nd ZMD America, Inc. 201 Old Country Road Suite 204 Melville, NY 11747 USA ZMD Japan 2 Floor, Shinbashi Tokyu Bldg. 4-21-3, Shinbashi, Minato-ku Tokyo, 105-0004 Japan Phone +81.3.6895.7410 Fax +81.3.6895.7301 sales@zmdi.com ZMD Far East 3F, No.,51, Sec. 2, Keelung Road 11052 Taipei Taiwan Phone +886.3.563.1388 Fax +886.3.563.6385 sales@zmdi.com +01 (631) 549-2666 Phone +49 (0)351.8822.7.772 Phone +01 (631) 549-2882 Fax +49(0)351.8822.87.772 Fax sales@zmdi.com sales@zmdi.com Data Sheet Rev. 1.06 October 2009 (c) 2009 ZMD AG Rev. 1.06 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is subject to changes without notice. 23 / 23 |
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